1. Field of the Invention
This invention relates to a semiconductor memory device suitable for reduction of power consumption.
2. Description of Related Art
Reduction of power consumption has become a major problem also in the technical field of semiconductor memory devices and, in this technical field, reduction of power consumption during power down mode is particularly desired. In order to achieve this, when a semiconductor memory device is placed in power down mode, the power consumption is reduced by stopping power supply to the semiconductor memory device, or by stopping clocks. Deep power down (DPD) mode is one of such power down mode, in which power supply to a memory cell array in a semiconductor memory device is stopped while at the same time stopping clocks. During deep power down mode, all the input buffers except clock and clock enable buffers are stopped. When the semiconductor memory device is a DRAM (Dynamic Random Access Memory), refresh of memory cells in the memory cell array is also stopped during deep power down mode. Therefore, when the semiconductor memory device is a DRAM, data in the memory cells of the memory cell array is not held in the memory cells since accumulated electric charge is discharged. Thus, the deep power down mode is a mode which does not ensure retention of data in the memory cells.
Referring to FIG. 6, a related art of the invention will be described specifically. FIG. 6 is a block diagram showing an example of a semiconductor memory device, that is made by the applicant of this application for explaining the related art of the invention. FIG. 6A is a block diagram illustrating a relationship between main IO lines (input/output lines) (hereafter, referred to as the MIO lines) and local IO lines (hereafter, referred to as the LIO lines) in a DRAM cell array. FIG. 6B is a block diagram showing a relationship between a DRAM cell array 5 composed of a plurality of the memory cells (i.e. DRAM cells) 101 shown in FIG. 6A, a peripheral circuit and a power supply circuit. FIG. 6C is a circuit diagram showing a configuration example of the power supply control circuit A 801 shown in FIG. 6B.
As shown in FIG. 6A, a LOCAL-IO (T) 91 that is a data noninverting (T) local IO line and a LOCAL-IO (B) 92 that is a data inverting (B) local IO line connected to the memory cell 101 are connected to a MAIN-IO (T) 81 that is a data noninverting (T) main IO line and a MAIN-IO (B) 82 that is a data inverting (B) main IO line via transistors (n-channel MOS (metal-oxide semiconductor) transistors) T6 and T7, respectively. The transistors T6 and T7 are turned on or off by a control signal LMIOSW output by a row decoder (XDEC) not shown in the drawing.
As shown in FIG. 6B, power is supplied to an internal power supply circuit 601 and a power supply control circuit A 801 from an external power supply 501. The internal power supply circuit 601 supplied with power from the external power supply 501 outputs a supply voltage VARY and a precharging voltage hVcc to the memory cell array 5. This precharging voltage hVcc is of a magnitude corresponding to a half of a power supply voltage Vcc. The power supply control circuit A 801 converts the voltage output by the external power supply 501 to a supply voltage VPERI that is output to a peripheral circuit. When a deep power down signal is “H” level (i.e. during deep power down mode), the internal power supply circuit 601 reduces the voltage VARY and the voltage hVcc to the ground Vss level (or shuts down the output current), while the power supply control circuit A 801 reduces the voltage VPERI to the ground Vss level (or shuts down the output current).
The power supply voltage Vcc has substantially the same voltage value as that of the external power supply 501 (even though the voltage may drop due to a protection element or wiring inserted in the line), and is a voltage that is constantly supplied from the external power supply 501.
The memory cell array 5 is composed of a plurality of the memory cells 101 shown in FIG. 6A. The peripheral circuit 401 includes a column decoder (YDEC), a row decoder (XDEC), various buffer circuits, a command decoder, an address decoder, and the like. A MIO line pair 8 and the like are wired from the memory cell array 5 to the peripheral circuit 401. The MIO line pair 8 is composed of a MAIN-IO (T) 81 and a MAIN-IO (B) 82.
The power supply control circuit A 801 shown in FIG. 6B is composed of inverter s G21 and G22 and a p-channel MOS transistor T21 which are serially connected as shown in a simplified manner in FIG. 6C. A deep power down signal is input to an input of the inverter G21, and an output of the inverter G22 is connected to a gate of the transistor T21. A source of the transistor T21 is connected to the power supply Vcc, and the supply voltage VPERI is output from a drain of the transistor T21 to the peripheral circuit. When the deep power down signal becomes “L” level, the transistor T21 is turned on to output the voltage VPERI, whereas when the deep power down signal becomes “H level, the transistor T21 is turned off and the wiring of the power supply voltage Vcc becomes electrically disconnected from the wiring of the voltage VPERI. As a result, no current is supplied to the wiring of the voltage VPERI from the wiring of the power supply voltage Vcc.
In the semiconductor memory device shown in FIG. 6B, the VARY (supply voltage to the memory cell array), the hVcc (precharging voltage), and the VPERI (supply voltage to the peripheral circuit) are not supplied from the internal power supply circuit 601 and power supply control circuit A 801 during deep power down mode, due to the same configuration for the voltage VPERI shown in FIG. 6C.
However, as shown in FIG. 6C in a simplified manner, the power supply control circuit A 801 requires a switching element consisting of a transistor (i.e. the transistor T21). This switching element is formed in a large size according to a magnitude of current supplied to the peripheral circuit as a whole. Therefore, there is also a demand for eliminating this switching element for the purpose of reducing the chip area.